RSD 09/2018
Russian Supercomputing Days 2018 was held on Semptember 24th - 25th, 2018 in Russia, Moscow, hotel Holiday Inn Moscow - Sokolniki.
N.A. Kataev has proposed there a speaker paper:
Application of the LLVM Compiler Infrastructure to the Program Analysis in SAPFOR
The paper proposes an approach to implementation of program analysis in SAPFOR (System FOR Automated Parallelization). This is a software development suit that is focused on cost reduction of manual program parallelization. It was primarily designed to perform source-to-source transformation of a sequential program for execution on parallel architectures with distributed memory. LLVM (Low Level Virtual Machine) compiler infrastructure is used to examine a program. This paper focuses on establishing a correspondence between the properties of the program in the programming language and the properties of its low-level representation.
The reported study was funded by the Program of the Presidium of RAS 26 “Fundamental basis for creating algorithms and software for perspective ultrahigh-performance computing”.
This article is written by N.A. Kataev.
V.A. Bakhtin has proposed there a speaker paper:
Incremental parallelization of programs using DVM-system
The main difficulty of a parallel program development for the cluster is the need to make global decisions on the distribution of data and calculations, taking into account the properties of the entire program, and then perform painstaking work on its modifying and debugging. A large amount of code, multi-modularity, multifunctionality makes it difficult to make decisions on the coordinated distribution of data and calculations. The method of incremental or partial parallelization can be used to solve this problem. The idea of this method is not the whole program is parallelized, but its parts (areas of parallelization) – the additional instances of the required data are created in them, the distribution of this data and the corresponding calculations is performed. These areas can be built on the basis of the times obtained by the performance analyzer, which is the part of DVM-system.
This article is written by a team of the following authors V.A. Bakhtin, V.A. Krukov, N.V. Podderugina, M.N. Pritula, D.A. Zaharov.