Parallelization of NAS NPB3.3.1 tests on Fortran-DVMH for Intel Xeon Phi coproccessor
Authors
V.F. Aleksahin, V.A. Bakhtin, A.S. Kolganov, V.A. Krukov, I.P. Ostrovskaya, N.V. Podderugina, M.N. Pritula, O.A. Savitskaya, O.F. Zhukova
Annotation
The article analyzes the efficiency of the implementation of NAS benchmarks from NPB 3.3.1 package (EP, MG, BT, SP, LU) on cluster nodes with different architectures using multi-cores processors, NVidia graphics accelerators and Intel coprocessors. Characteristics of the tests developed in high-level Fortran-DVMH language (hereafter referred to as FDVMH), and their implementations in other languages are compared. The effect of different optimization methods for FDVMH NAS benchmarks necessary for their effective work in Intel Xeon Phi coprocessor is researched. The results of the simultaneous using of all cores in CPU, GPU and Intel Xeon Phi coprocessor are presented.
Key words
DVMH, high-level programming language, accelerator, coprocessor, GPU, NAS Parallel Benchmarks, Fortran.
Language
English
Presented on
Reference
V.F. Aleksahin, V.A. Bakhtin, A.S. Kolganov, V.A. Krukov, I.P. Ostrovskaya, N.V. Podderugina, M.N. Pritula, O.A. Savitskaya, O.F. Zhukova. Parallelization of NAS NPB3.3.1 tests on Fortran-DVMH for Intel Xeon Phi coproccessor // Proceedings of the international scientific conference "Parallel Computational Technologies (PCT'2015)", Chelyabinsk: null, 2015, P. 19-30